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19-1337; Rev 0; 2/98
KIT ATION EVALU ABLE AVAIL
High-Speed Step-Down Controller with Synchronous Rectification for CPU Power
________________General Description
The MAX1639 is an ultra-high-performance, step-down DC-DC controller for CPU power in high-end computer systems. Designed for demanding applications in which output voltage precision and good transient response are critical for proper operation, it delivers over 35A from 1.1V to 4.5V with 1% total accuracy from a +5V 10% supply. Excellent dynamic response corrects output transients caused by the latest dynamically clocked CPUs. This controller achieves over 90% efficiency by using synchronous rectification. Flying-capacitor bootstrap circuitry drives inexpensive, external N-channel MOSFETs. The switching frequency is pin-selectable for 300kHz, 600kHz, or 1MHz. High switching frequencies allow the use of a small surface-mount inductor and decrease output filter capacitor requirements, reducing board area and system cost. Output overvoltage protection is enforced by a crowbar circuit that turns on the low-side MOSFET with 100% duty factor when the output is 200mV above the normal regulation point. Other features include internal digital soft-start, a power-good output, and a 3.5V 1% reference output. The MAX1639 is available in a 16-pin narrow SOIC package.
____________________________Features
o Better than 1% Output Accuracy Over Line and Load o Greater than 90% Efficiency Using N-Channel MOSFETs o Pin-Selected High Switching Frequency: 300kHz, 600kHz, or 1MHz o Over 35A Output Current o Resistor-Divider Adjustable Output from 1.1V to 4.5V o Current-Mode Control for Fast Transient Response and Cycle-by-Cycle Current-Limit Protection o Short-Circuit Protection with Foldback Current Limiting o Crowbar Overvoltage Protection o Power-Good (PWROK) Output o Digital Soft-Start o High-Current (2A) Drive Outputs
MAX1639
________________________Applications
Local DC-DC Converters for CPUs Workstations Desktop Computers LAN Servers GTL Bus Termination
__________ Typical Operating Circuit
INPUT +5V VCC AGND TO VDD VDD BST
MAX1639 DH
LX PWROK OUTPUT 1.1V TO 4.5V
_______________Ordering Information
PART MAX1639ESE TEMP. RANGE -40C to +85C PIN-PACKAGE 16 Narrow SO
REF
DL PGND
CSH CSL
Pin Configuration appears at end of data sheet.
FREQ CC1 CC2 FB
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.
High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1639
ABSOLUTE MAXIMUM RATINGS
VDD, VCC, PWROK to AGND....................................-0.3V to +6V PGND to AGND ..................................................................0.3V CSH, CSL to AGND ....................................-0.3V to (VCC + 0.3V) DL to PGND................................................-0.3V to (VDD + 0.3V) REF, CC1, CC2, FREQ, FB to AGND .........-0.3V to (VCC + 0.3V) BST to PGND..........................................................-0.3V to +12V BST to LX..................................................................-0.3V to +6V DH to LX.............................................(LX - 0.3V) to (BST + 0.3V) Continuous Power Dissipation (TA = +70C) 16-Pin Narrow SO (derate 8.70mW/C above +70C) ....696mW SO JC ...........................................................................65C/W Operating Temperature Range MAX1639ESE....................................................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VCC = +5V, PGND = AGND = 0V, FREQ = REF, TA = 0C to +85C, unless otherwise noted.) PARAMETER FB Voltage Input Voltage Range Input Undervoltage Lockout CONDITIONS Includes line and load regulation errors VCC = VDD VCC rising edge, 1% hysteresis VCC = VDD = 5.5V Operating mode Shutdown mode FB overdrive = 60mV FB overdrive = 0V VREF = 0V 5 3.6 10 0.1 3.465 2.7 0.5 1 0.1 -7.5 6.5 -6 8 -4.5 9.5 0.4 1 850 540 255 85 3.3 VCC - 0.1 1000 600 300 90 0.2 3.7 V 1150 660 345 % kHz 3.5 3.535 10 3.0 4.0 mA V mV V mA % % % V A TA = +25C to +85C TA = 0C to +85C MIN 1.089 1.083 4.5 4.0 TYP MAX 1.111 1.117 5.5 4.2 2.5 mA UNITS V V V
VCC Supply Current (ICC)
VDD Supply Current (IDD) Reference Voltage Reference Load Regulation Reference Undervoltage Lockout Reference Short-Circuit Current AC Load Regulation DC Load Regulation PWROK Trip Level PWROK Output Voltage Low PWROK Output Current High Switching Frequency Maximum Duty Cycle FREQ Input Voltage FREQ Input Voltage
VCC = VDD = 5.5V, FB forced 60mV above regulation point, operating or standby mode No load 0A < IREF < 100A Rising edge, 1% hysteresis VREF = 0V CSH - CSL = 0mV to 80mV CSH - CSL = 0mV to 80mV Rising FB, 1% hysteresis with respect to VREF Falling FB, 1% hysteresis with respect to VREF ISINK = 2mA, VCC = 4.5V PWROK = 5.5V FREQ = VCC FREQ = REF FREQ = AGND FREQ = VCC GND (low) REF (mid) VCC (high)
2
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1639
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VCC = +5V, PGND = AGND = 0V, FREQ = REF, TA = 0C to +85C, unless otherwise noted.) PARAMETER FREQ Input Current CSH, CSL Input Current FB Input Current CC1 Output Resistance CC2 Transconductance CC2 Clamp Voltage CC2 Source/Sink Current DH On-Resistance DL On-Resistance DH, DL Source/Sink Current DH, DL Dead Time Current-Limit Trip Voltage Soft-Start Time BST Leakage Current FB = 1.1V FB = 0V (foldback) To full current limit BST = 12V, LX = 7V, REF = GND Minimum Maximum 30mV overdrive BST - LX = 4.5V VDD = 4.5V DH = DL = 2.5V 0 85 15 2.4 4 100 0.7 0.7 2 30 100 38 1536 50 115 70 2 2 10 1 3.0 VCC CSH = CSL = 1.1V CONDITIONS MIN TYP MAX 4 50 0.1 UNITS A A A k mmho V A A ns mV 1 / fOSC A
ELECTRICAL CHARACTERISTICS
(VDD = VCC = +5V, PGND = AGND = 0V, FREQ = REF, TA = -40C to +85C, unless otherwise noted.) (Note 1) PARAMETER Input Voltage Range Input Undervoltage Range VDD Supply Current VDD Supply Current Reference Voltage FB Voltage PWROK Trip Level VCC = VDD VCC rising edge, 1% hysteresis VCC = VDD = 5.5V Operating mode Shutdown mode FB overdrive = 60mV VREF = 0V CONDITIONS MIN 4.5 3.9 TYP MAX 5.5 4.3 3 12 0.2 3.448 1.072 -8 6 800 510 240 84 2 2 70 130 3.553 1.128 -4 10 1200 690 360 % mV kHz UNITS V V mA mA V V %
VCC = VDD = 5.5V, FB forced 60mV above regulation point, operating or shutdown mode No load Includes line and load regulation errors Rising FB, 1% hysteresis with respect to VREF Falling FB, 1% hysteresis with respect to VREF FREQ = VCC FREQ = REF FREQ = AGND FREQ = VCC BST - LX = 4.5V VDD = 4.5V FB = 1.1V
Switching Frequency Maximum Duty Cycle DH On-Resistance DL On-Resistance Current-Limit Trip Voltage
Note 1: Specifications from 0C to -40C are guaranteed by design, not production tested.
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1639
__________________________________________Typical Operating Characteristics
(TA = +25C, using the MAX1639 evaluation kit, unless otherwise noted.)
LOAD-TRANSIENT RESPONSE (VOUT = 2.5V)
MAX1639-01
FOLDBACK CURRENT LIMIT (VOUT = 2.5V, NOMINAL)
MAX1639-02
START-UP WAVEFORMS
MAX1639-03
A
A
A B B 10s/div VIN = 5V, VOUT = 2.5V, LOAD = 8A A: VOUT, 100mV/div, AC COUPLED B: INDUCTOR CURRENT, 5A/div 10s/div A: VOUT = 0.5V/div B: INDUCTOR CURRENT, 5A/div B 400s/div A: INDUCTOR CURRENT, 2A/div B: VOUT = 1V/div
SWITCHING WAVEFORMS
MAX1639-04
EFFICIENCY vs. OUTPUT CURRENT
MAX1639-05
MAXIMUM DUTY CYCLE vs. SWITCHING FREQUENCY
95 MAXIMUM DUTY CYCLE (%) 90 85 80 75 70 65 60 55
MAX1639-06
100 3.5V 90 EFFICIENCY (%) 2.5V 80 1.8V 70
100
A
B
C 0
60
50 1s/div VIN = 5V, VOUT = 2.5V, LOAD = 0A A: VOUT, 20mV/div B: INDUCTOR CURRENT, 2A/div C: LX, 5V/div 0.1 1 OUTPUT CURRENT (A) 10
50 0 200 400 600 800 1000 1200 SWITCHING FREQUENCY (kHz)
4
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME BST PWROK CSL CSH VCC REF AGND FB CC1 CC2 FUNCTION Boost-Capacitor Bypass for High-Side MOSFET Gate Drive. Connect a 0.1F capacitor and low-leakage Schottky diode as a bootstrapped charge-pump circuit to derive a 5V gate drive from VDD for DH. Open-Drain Logic Output. PWROK is high when the voltage on FB is within +8% and -6% of its setpoint. Current-Sense Amplifier's Inverting Input. Place the current-sense resistor very close to the controller IC, and use a Kelvin connection. Current-Sense Amplifier's Noninverting Input Analog Supply Input, 5V. Use an RC filter network, as shown in Figure 1. Reference Output, 3.5V. Bypass REF to AGND with 0.1F (min). Sources up to 100A for external loads. Force REF below 2V to turn off the controller. Analog Ground Voltage-Feedback Input. The voltage at this input is regulated to 1.100V. Fast-Loop Compensation Capacitor Input. Connect a ceramic capacitor and resistor in series from CC1 to AGND. See the section Compensating the Feedback Loop. Slow-Loop Compensation Capacitor Input. Connect a ceramic capacitor from CC2 to AGND. See the section Compensating the Feedback Loop. Frequency-Select Input. FREQ = VCC: 1MHz FREQ = REF: 600kHz FREQ = AGND: 300kHz Power Input for MOSFET Drivers, 5V. Bypass VDD to PGND within 0.2 in. (5mm) of the VDD pin using a 0.1F capacitor and 4.7F capacitor connected in parallel. Low-Side Synchronous Rectifier Gate-Drive Output. DL swings between PGND and VDD. See the section BST High-Side Gate-Driver Supply and MOSFET Drivers. Power Ground Switching Node. Connect LX to the high-side MOSFET source and inductor. High-Side Main MOSFET Switch Gate-Drive Output. DH is a floating driver output that swings from LX to BST, riding on the LX switching-node voltage. See the section BST High-Side Gate-Driver Supply and MOSFET Drivers.
MAX1639
11
FREQ
12 13 14 15 16
VDD DL PGND LX DH
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1639
_______Standard Application Circuits
The predesigned MAX1639 circuit shown in Figure 1 meets a wide range of applications with output currents up to 35A. Use Table 1 to select components appropriate for the desired output current range, and adapt the evaluation kit PC board layout as necessary. This circuit represents a good set of trade-offs between cost, size, and efficiency while staying within the worst-case specification limits for stress-related parameters, such as capacitor ripple current. The MAX1639 circuit was designed for the specified frequencies. Do not change the switching frequency without first recalculating component values--particularly the inductance, output filter capacitance, and RC1 resistance values.
___________________Detailed Description
The MAX1639 is a BiCMOS power-supply controller designed for use in switch-mode, step-down (buck) topology DC-DC converters. Synchronous rectification provides high efficiency. It is intended to provide the high precision, low noise, excellent transient response, and high efficiency required in today's most demanding applications.
R5 10 C5 0.1F C6 10F TO VDD R6 100k PWROK BST C3 0.1F VCC VDD C7 0.1F D2 CMPSH-3
VIN = 4.5V TO 5.5V C1
DH R4 (OPTIONAL) LX
N1
L1 R1 R3 (OPTIONAL) D1 (OPTIONAL)
MAX1639
VOUT = 1.1V TO 4.5V C2
DL FREQ REF C4, 1.0F CERAMIC CC2 CC2 RC1 0.056F 1k CC1 CC1 1000pF AGND PGND CSH CSL
N2
R7 FB R8 C8
TO AGND
Figure 1. Standard Application Circuit
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power
Table 1. Component List for Standard Applications
COMPONENT C1 C2 D1 (optional) D2 L1 LOAD REQUIREMENT 2.5V, 8A 330F, Sanyo OS-CON 6SA330M (x2) 560F, Sanyo OS-CON 4SP560M Schottky diode, Nihon NSQ03A02 Central Semiconductor CMPSH-3 1.0H, 9.3A, SMD Coiltronics UP2B-1R0 1.0H, 10A, SMD Coilcraft D03316P-102HC 0.014, 30V, SO8 Fairchild FDS6680 0.018, 30V, SO8 International Rectifier IRF7413 0.014, 30V, SO8 Fairchild FDS6680 0.018, 30V, SO8 International Rectifier IRF7413 9m Dale, WSL-2512-R009-J 10.0k, 1% 12.7k, 1% 1.8V, 20A (x3) 330F, Sanyo OS-CON 6SA330M (x5) 560F, Sanyo OS-CON 4SP560M Schottky diode, Motorola MBRD640 Central Semiconductor CMPSH-3 0.3H, 25A, 0.9m Panasonic ETQPAF0R3E
MAX1639
N1
(x2) 0.010, 30V, D2 PAK, Fairchild FDB7030L (x2) 0.014, 30V, SO8, Fairchild FDS6680
N2
(x2) 0.010, 30V, D2 PAK, Fairchild FDB7030L (x2) 0.014, 30V, SO8, Fairchild FDS6680 (x2) 7m, Dale WSL-2512-R007-J 10.0k, 1% 6.19k, 1%
R1 R7 R8
Note: Parts used in evaluation board are shown in bold.
PWM Controller Block and Integrator
The heart of the current-mode PWM controller is a multi-input, open-loop comparator that sums three signals (Figure 2): the buffered feedback signal, the current-sense signal, and the slope-compensation ramp. This direct-summing configuration approaches ideal cycle-by-cycle control over the output voltage. The output voltage error signal is generated by an error amplifier that compares the amplified feedback voltage to an internal reference. Each pulse from the oscillator sets the main PWM latch that turns on the high-side switch for a period determined by the duty factor (approximately VOUT / VIN). The current-mode feedback system regulates the peak inductor current as a function of the output voltage error signal. Since average inductor current is nearly the same as peak current (assuming the inductor value is set relatively high to minimize ripple current), the circuit acts as a switch-mode transconductance amplifier. It pushes the second output LC filter pole, normally found in a dutyfactor-controlled (voltage-mode) PWM, to a higher frequency. To preserve inner-loop stability and eliminate regenerative inductor current staircasing, a slopecompensation ramp is summed into the main PWM comparator. Under fault conditions where the inductor current exceeds the maximum current-limit threshold, the high-side latch resets, and the high-side switch turns off.
Internal Reference
The internal 3.5V reference (REF) is accurate to 1% from 0C to +85C, making REF useful as a system reference. Bypass REF to AGND with a 0.1F (min) ceramic capacitor. A larger value (such as 2.2F) is recommended for high-current applications. Load regulation is 10mV for loads up to 100A. Reference undervoltage lockout is between 2.7V and 3V. Shortcircuit current is less than 4mA.
Synchronous-Rectifier Driver
Synchronous rectification reduces conduction losses in the rectifier by shunting the normal Schottky diode or MOSFET body diode with a low-on-resistance MOSFET switch. The synchronous rectifier also ensures proper start-up by precharging the boost-charge pump used for the high-side switch gate-drive circuit. Thus, if you must omit the synchronous power MOSFET for cost or other reasons, replace it with a small-signal MOSFET, such as a 2N7002. The DL drive waveform is simply the complement of the DH high-side drive waveform (with typical controlled dead time of 30ns to prevent cross-conduction or shoot-through). The DL output's on-resistance is 0.7 (typ) and 2 (max).
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1639
REF
REF1
REF2
CSL
AGND
MAX1639
SLOPE COMPENSATION
VCC
FREQ
OSCILLATOR REF
RESET CONTROL AND DRIVE LOGIC
Q
Q SET CC1 40k CC2 10k WINDOW REF2 REF REF1 24R 11R N
gm
FB
PWROK
Figure 2. Simplified Block Diagram
8
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+ -
CSH
BST DH
LX
VDD DL PGND
High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1639
BST High-Side Gate-Driver Supply and MOSFET Drivers
Gate-drive voltage for the high-side N-channel switch is generated using a flying-capacitor boost circuit (Figure 3). The capacitor is alternately charged from the +5V supply and placed in parallel with the highside MOSFET's gate and source terminals. Gate-drive resistors (R3 and R4) can often be useful to reduce jitter in the switching waveforms by slowing down the fast-slewing LX node and reducing ground bounce at the controller IC. However, switching loss may increase. Low-value resistors from around 1 to 5 are sufficient for many applications.
BST LEVEL TRANSLATOR DH LX VDD CONTROL AND DRIVE LOGIC DL R3 PGND N2 R4 L1 N1 C3 VIN = 5V D2 C1
Current Sense and Overload Current Limiting
The current-sense circuit resets the main PWM latch and turns off the high-side MOSFET switch whenever the voltage difference between CSH and CSL from current through the sense resistor (R1) exceeds the peak current limit (100mV typical). Current-mode control provides cycle-by-cycle currentlimit capability for maximum overload protection. During normal operation, the peak current limit set by the current-sense resistor determines the maximum output current. When the output is shorted, the peak current may be higher than the set current limit due to delays in the current-sense comparator. Thus, foldback current limiting is employed where the set current-limit point is reduced from 100mV to 38mV as the output (feedback) voltage falls (Figure 4). When the shortcircuit condition is removed, the feedback voltage will rise and the current-limit voltage will revert to 100mV. The foldback current-limit circuit is designed to ensure startup into a resistive load.
MAX1639
R3 AND R4 ARE OPTIONAL
Figure 3. Boost Supply for Gate Drivers
100 90 80 70 ILIM (%) 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 VFB (%)
High-Side Current Sensing
The common-mode input range of the current-sense inputs (CSH and CSL) extends to VCC, so it is possible to configure the circuit with the current-sense resistor on the input side rather than on the load side (Figure 5). This configuration improves efficiency by reducing the power dissipation in the sense resistor according to the duty ratio. In the high-side configuration, if the output is shorted directly to GND through a low-resistance path, the current-sense comparator may be unable to enforce a current limit. Under such conditions, circuit parasitics such as MOSFET R DS(ON) typically limit the shortcircuit current to a value around the peak-currentlimit setting.
Figure 4. Foldback Current Limit
Attach a lowpass-filter network between the currentsense pins and resistor to reduce high-frequency common-mode noise. The filter should be designed with a time constant of around one-fifth of the on-time (130ns at 600kHz, for example). Resistors in the 20 to 100 range are recommended for R9 and R10. Connect the filter capacitors C9 and C10 from VCC to CSH and CSL, respectively. Values of 39 and 3.3nF are suitable for many designs. Place the current-sense filter network close to the IC, within 0.1 in (2.5mm) of the CSH and CSL pins.
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1639
Overvoltage Protection
When the output exceeds the set voltage, the synchronous rectifier output (DL) is driven high (and DH is driven low). This causes the inductor to quickly dissipate any stored energy and force the fault current to flow to ground. Current is limited by the source impedance and parasitic resistance of the current path, so a fuse is required in series with the +5V input to protect against low-impedance faults, such as a shorted high-side MOSFET. Otherwise, the low-side MOSFET will eventually fail. DL will go low if the input voltage drops below the undervoltage lockout point.
R5 10
VIN
C5 0.1F
C6 10F C9 4.7nF CSH R9 39
C1
VCC C10 4.7nF
Internal Soft-Start
Soft-start allows a gradual increase of the internal current limit at start-up to reduce input surge currents. An internal DAC raises the current-limit threshold from 0V to 100mV in four steps (25mV, 50mV, 75mV, and 100mV) over the span of 1536 oscillator cycles.
MAX1639
CSL
R1
R10 39 N1
__________________Design Procedure
Setting the Output Voltage
Set the output voltage by connecting R7 and R8 (Figure 6) to the FB pin from the output to AGND. R7 is given by the following equation: V R7 = R8 x OUT - 1 VFB where VFB = 1.1V. Since the input bias current at FB has a maximum value of 0.1A, values up to 10k can be used for R8 with no significant accuracy loss. Values under 1k are recommended to improve noise immunity. Place R7 and R8 very close to the MAX1639, within 0.2in (5mm) of the FB pin.
C8 (OPTIONAL) VOUT FB R7
Figure 5. High-Side Current Sense
MAX1639
AGND
R8
LOAD
Feed-Forward Compensation
An optional compensation capacitor (C8), typically 220pF, may be needed across the upper feedback resistor to counter the effects of stray capacitance on the FB pin, and to help ensure stable operation when highvalue feedback resistors are used (Figure 6). Empirically adjust the feed-forward capacitor as needed.
PLACE VERY CLOSE TO MAX1639
Specifying the Inductor
Three key inductor parameters must be specified: inductance value (L), peak current (IPEAK), and DC resistance (RDC). The following equation includes a constant LIR, which is the ratio of inductor peak-topeak AC current to DC load current. Typically LIR can be between 0.1 to 0.5. A higher LIR value allows for smaller inductors and better transient response, but
10
Figure 6. Output Selection
results in higher losses and output ripple. A good compromise between size and loss is a 30% ripple current to load current ratio (LIR = 0.30), which corresponds to a peak inductor current 1.15 times higher than the DC load current.
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power
L= VOUT VIN(MAX) - VOUT
(
)
In high-current applications, connect several resistors in parallel as necessary to obtain the desired resistance and power rating.
MAX1639
VIN(MAX) x fOSC x IOUT x LIR
Selecting the Output Filter Capacitor
Output filter capacitor values are generally determined by effective series resistance (ESR) and voltage-rating requirements, rather than by the actual capacitance value required for loop stability. Due to the high switching currents and demanding regulation requirements in a typical MAX1639 application, use only specialized low-ESR capacitors intended for switchingregulator applications, such as AVX TPS, Kemet T510, Sprague 595D, Sanyo OS-CON, or Sanyo GX series. Do not use standard aluminum-electrolytic capacitors, which can cause high output ripple and instability due to high ESR. The output voltage ripple is usually dominated by the filter capacitor's ESR, and can be approximated as I RIPPLE x R ESR . To ensure stability, the capacitor must meet both minimum capacitance and maximum ESR values as given in the following equations: VOUT VREF 1 + VIN(MIN) VOUT x RSENSE x fOSC
where f is the switching frequency, between 300kHz and 1MHz; IOUT is the maximum DC load current; and LIR is the ratio of AC to DC inductor current (typically 0.3). The exact inductor value is not critical and can be adjusted to make trade-offs among size, transient response, cost, and efficiency. Although lower inductor values minimize size and cost, they also reduce efficiency due to higher peak currents. In general, higher inductor values increase efficiency, but at some point resistive losses due to extra turns of wire exceed the benefit gained from lower AC current levels. Loadtransient response can be adversely affected by high inductor values, especially at low (VIN - VOUT) differentials. The peak inductor current at full load is 1.15 x IOUT if the previous equation is used; otherwise, the peak current can be calculated using the following equation: VOUT VIN(MAX) - VOUT 2fOSC x L x VIN(MAX)
IPEAK = IOUT +
(
)
COUT >
The inductor's DC resistance is a key parameter for efficient performance, and should be less than the currentsense resistor value.
RESR < RSENSE
Calculating the Current-Sense Resistor Value
Calculate the current-sense resistor value according to the worst-case minimum current-limit threshold voltage (from the Electrical Characteristics) and the peak inductor current required to service the maximum load. Use IPEAK from the equation in the section Specifying the Inductor. RSENSE = 85mV IPEAK
Compensating the Feedback Loop
The feedback loop needs proper compensation to prevent excessive output ripple and poor efficiency caused by instability. Compensation cancels unwanted poles and zeros in the DC-DC converter's transfer function that are due to the power-switching and filter elements with corresponding zeros and poles in the feedback network. These compensation zeros and poles are set by the compensation components CC1, CC2, and RC1. The objective of compensation is to ensure stability by ensuring that the DC-DC converter's phase shift is less than 180 by a safe margin, at the frequency where the loop gain falls below unity.
The high inductance of standard wire-wound resistors can degrade performance. Low-inductance resistors, such as surface-mount power metal-strip resistors, are preferred. The current-sense resistor's power rating should be higher than the following: IOUT(MAX) 2 x RSENSE
Canceling the Sampling Pole and Output Filter ESR Zero Compensate the fast-voltage feedback loop by connecting a resistor and a capacitor in series from the CC1 pin to AGND. The pole from CC1 can be set to cancel the zero from the filter-capacitor ESR. Thus the capacitor at CC1 should be as follows:
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power MAX1639
CC1 = COUT x RESR 10k PD (low side) = ILOAD
2
V x RDS(ON) x 1 - OUT VIN
Resistor RC1 sets a zero that can be used to compensate for the sampling pole generated by the switching frequency. Set RC1 to the following: VOUT 1 + V IN 2fOSC x CC1
RC1 =
Gate-charge losses are dissipated in the IC, and do not heat the MOSFETs. Ensure that both MOSFETs are at a safe junction temperature by calculating the temperature rise according to package thermal-resistance specifications. The high-side MOSFET's worst-case dissipation occurs at the maximum output voltage and minimum input voltage. For the low-side MOSFET, the worst case is at the maximum input voltage when the output is shortcircuited (consider the duty factor to be 100%).
The CC1 pin's output resistance is 10k.
Calculating IC Power Dissipation
Power dissipation in the IC is dominated by average gate-charge current into both MOSFETs. Average current is approximately: IDD = (QG1 + QG2) x fOSC where I DD is the drive current, Q G is the total gate charge for each MOSFET, and fOSC is the switching frequency. Power dissipation of the IC is: PD = ICC x VCC + IDD x VDD where ICC is the quiescent supply current of the IC. Junction temperature for the IC is primarily a function of the PC board layout, since most of the heat is removed through the traces connected to the pins and the ground and power planes. A 16-pin narrow SO on a typical four-layer board with ground and power planes show equivalent junction-to-ambient thermal impedance of (JA) about 80C/W. Junction temperature of the die is approximately: TJ = PD x JA + TA where TA is the ambient temperature.
Setting the Dominant Pole and Canceling the Load and Output Filter Pole Compensate the slow-voltage feedback loop by adding a ceramic capacitor from the CC2 pin to AGND. This is an integrator loop used to cancel out the DC loadregulation error. Selection of capacitor CC2 sets the dominant pole and a compensation zero. The zero is typically used to cancel the unwanted pole generated by the load and output filter capacitor at the maximum load current. Select CC2 to place the zero close to or slightly lower than the frequency of the unwanted pole, as follows:
CC2 = 1mmho x COUT 4 x VOUT IOUT(MAX)
The transconductance of the integrator amplifier at CC2 is 1mmho. The voltage swing at CC2 is internally clamped around 2.4V to 3V minimum and 4V to VCC maximum to improve transient response times. CC2 can source and sink up to 100A.
Choosing the MOSFET Switches
The two high-current N-channel MOSFETs must be logic-level types with guaranteed on-resistance specifications at VGS = 4.5V. Lower gate-threshold specs are better (i.e., 2V max rather than 3V max). Gate charge should be less than 200nC to minimize switching losses and reduce power dissipation. I2R losses are the greatest heat contributor to MOSFET power dissipation and are distributed between the high- and low-side MOSFETs according to duty factor, as follows: PD (high side) = ILOAD
2
Selecting the Rectifier Diode
The rectifier diode D1 is a clamp that catches the negative inductor swing during the 30ns typical dead time between turning off the high-side MOSFET and turning on the low-side MOSFET synchronous rectifier. D1 must be a Schottky diode, to prevent the MOSFET body diode from conducting. It is acceptable to omit D1 and let the body diode clamp the negative inductor swing, but efficiency will drop about 1%. Use a 1N5819 diode for loads up to 3A, or a 1N5822 for loads up to 10A.
V x RDS(ON) x OUT VIN
Adding the BST Supply Diode and Capacitor
A signal diode, such as a 1N4148, works well for D2 in most applications, although a low-leakage Schottky diode provides slightly improved efficiency. Do not use
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High-Speed Step-Down Controller with Synchronous Rectification for CPU Power
large power diodes, such as the 1N4001 or 1N5817. Exercise caution in the selection of Schottky diodes, since some types exhibit high reverse leakage at high operating temperatures. Bypass BST to LX using a 0.1F capacitor. Place the high-power components (C1, R1, N1, D1, N2, L1, and C2 in Figure 1) as close together as possible. Minimize ground-trace lengths in high-current paths. The surface-mount power components should be butted up to one another with their ground terminals almost touching. Connect their ground terminals using a wide, filled zone of top-layer copper (the pseudoground plane), rather than through the internal ground plane. At the output terminal, use vias to connect the top-layer pseudo-ground plane to the normal innerlayer ground plane at the output filter capacitor ground terminals. This minimizes interference from IR drops and ground noise, and ensures that the IC's AGND is sensing at the supply's output terminals. Minimize high-current path trace lengths. Use very short and wide traces. From C1 to N1: 0.4 in. (10mm) max length; D1 anode to N2: 0.2 in. (5mm) max length; LX node (N1 source, N2 drain, D1 cathode, inductor L1): 0.6 in. (15mm) max length.
MAX1639
Selecting the Input Capacitors
Place a 0.1F ceramic capacitor and 10F capacitor between VCC and AGND, as well as between VDD and PGND, within 0.2 in. (5mm) of the VCC and VDD pins. Select low-ESR input filter capacitors with a ripplecurrent rating exceeding the RMS input ripple current, connecting several capacitors in parallel if necessary. RMS input ripple current is determined by the input voltage and load current, with the worst-possible case occurring at VIN = 2 x VOUT: IRMS = ILOAD (MAX) VOUT (VIN - VOUT ) VIN
IRMS = IOUT / 2 when VIN = 2VOUT
___________________Pin Configuration
__________Applications Information
Efficiency Considerations
Refer to the MAX796-MAX799 data sheet for information on calculating losses and improving efficiency.
TOP VIEW
BST 1 PWROK 2 CSL 3 CSH 4 VCC 5 REF 6 AGND 7 FB 8 16 DH 15 LX 14 PGND
PC Board Layout Considerations
Good PC board layout and routing are required in highcurrent, high-frequency switching power supplies to achieve good regulation, high efficiency, and stability. The PC board layout artist must be provided with explicit instructions concerning the placement of power-switching components and high-current routing. It is strongly recommended that the evaluation kit PC board layouts be followed as closely as possible. Contact Maxim's Applications Department concerning the availability of PC board examples for higher-current circuits. In most applications, the circuit is on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high-current power and ground connections. Leave the extra copper on the board as a pseudo-ground plane. Use the bottom layer for quiet connections (REF, FB, AGND), and the inner layers for an uninterrupted ground plane. A ground plane and pseudo-ground plane are essential for reducing ground bounce and switching noise.
MAX1639
13 DL 12 VDD 11 FREQ 10 CC2 9 CC1
16 SOIC
___________________Chip Information
TRANSISTOR COUNT: 3135 SUBSTRATE CONNECTED TO AGND
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